module hex8(
    input wire [3:0] x,
    output reg [6:0] dig
);

always @(*)
	case(x)
		0: dig = 7'b1000000;
		1: dig = 7'b1111001;
		2: dig = 7'b0100100;
		3: dig = 7'b0110000;
		4: dig = 7'b0011001;
		5: dig = 7'b0010010;
		6: dig = 7'b0000010;
		7: dig = 7'b1111000;
		8: dig = 7'b0000000;
		9: dig = 7'b0010000;
	   default: dig= 7'b1111111;// 0
	endcase
endmodule
